Korea University researchers have developed a machine-learning framework that predicts solar cell efficiency from wafer ...

TAIPEI, Taiwan--(BUSINESS WIRE)--TrendForce reports that the three largest DRAM suppliers are increasing wafer input for advanced processes. Following a rise in memory contract prices, companies have ...

Electronic devices have become an indispensable part of our lives in our technology-driven world. These devices owe their existence to a crucial component known as the semiconductor wafer. In this ...

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the ...

Flexibility: Applied’s most significant new platform in more than a decade hosts an unprecedented wide variety of chamber types, sizes and configurations, from Applied and partners Intelligence: ...

The global SiC Wafer Processing market size is projected to reach US$ 2,986.44 million by 2032, at a CAGR of 14.43% ...

NexWafe’s EpiNex solar wafers achieved 24.4% efficiency on a commercial M6 heterojunction (HJT) cell line, for the first time delivering performance parity with conventional CZ wafers. Modules made ...

Vitrek’s Cost-Sensitive Accumeasure Capacitance-Based Metrology System Simplifies the Development of Adaptable ...

BAY CITY, Mich. (AP) — The U.S. Department of Energy announced a conditional $544 million loan Thursday that would allow a Michigan semiconductor manufacturing plant to expand to make parts that can ...

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during ...

Rapidus on Friday announced that it had begun prototyping of test wafers with 2nm gate-all-around (GAA) transistor structures at its IIM-1 facility in Japan. The company confirmed that early test ...